AMD GPU compute · visual field guideAMD GPU 计算 · 可视化学习总览

ROCm Stack Atlas

Nine layers between an AMD GPU and a line of PyTorch — what each one owns, what it is called in the source tree, and the path a single kernel launch actually takes through them. 从 AMD GPU 到一行 PyTorch 之间的九个层次:每层负责什么、在源码树里叫什么名字,以及一次 kernel 启动真正走过的路径。

Release
ROCm Core SDK 7.14.0
Dated
2026-08-31
Built by
TheRock
signal path specimen · 01 ROCm stack cutaway from PyTorch to AMD GPU silicon Applications and frameworks sit above HIP, tuned libraries and ROCr. The per-launch path reaches the GPU through an AQL queue and mapped doorbell; KFD setup and the compiler are separate side paths. ROCM / END-TO-END COMPUTE 08 · OBSERVABILITY SPANS ALL LAYERS 09 Apps · 07 Frameworks workloads · graphs · ops 05 Libraries · 04 HIP two layers · shared hot path 03 ROCr runtime AQL queue + signal 02 KFD queue setup GPUVM · mapped doorbell tensor op /dev/kfd boundary MAPPED MMIO · NO SYSCALL 01 · GPU PACKAGE SETUP / EXCEPTIONS 06 · BUILD RAIL Clang / LLVM gfx code object

What ROCm isROCm 是什么

An open-source software stack of runtimes, compiler, libraries and tools that lets C++, Python and AI code reach AMD GPUs. This atlas widens the view to the hardware and driver below ROCm, and the frameworks and applications above it. 一套由运行时、编译器、数学库与工具组成的开源软件栈,让 C++、Python 与 AI 代码到达 AMD GPU。本图进一步把 ROCm 下方的硬件与驱动,以及上方的框架与应用一并纳入视野。

The boundary that matters最关键的边界

Everything above /dev/kfd is user space. The kernel driver establishes and manages queue resources; after setup, a steady-state direct launch can be a packet plus a doorbell — normally no submit syscall per dispatch. Faults and lifecycle events can still re-enter the kernel. /dev/kfd 之上全是用户态。内核驱动负责建立并管理队列资源;设置完成后,稳态直接启动可以只是写 packet 再敲 doorbell —— 通常无需每次派发 submit syscall。缺页与生命周期事件仍可能再次进入内核。

How to read the colours如何阅读配色

Below you — platform & kernel space你之下:硬件与内核态
Where you write code你写代码的地方
Above you — consumers & tooling你之上:框架、工具与应用
CASE

Solve one GPU job, frame by frame先解一道题:逐帧看懂一次 GPU 工作

2 × 2 matrix multiply · correctness, not performance2 × 2 矩阵乘法 · 用于理解正确性,不代表性能

Worked example 00 · naive HIP kernel完整案例 00 · 手写朴素 HIP kernel

Given A and B, make the GPU compute C = A × B.给定 A 和 B,让 GPU 算出 C = A × B。

We will follow A and B's eight input values from CPU memory, through compilation and a user-mode queue, into four GPU work-items, then back to a result the CPU can verify. Use Previous/Next, or jump to any step. 我们会追踪同一组数据:从 CPU 内存出发,经过编译与用户态队列,交给 4 个 GPU 工作项,最后回到 CPU 验证结果。可用上一步/下一步,也可直接跳到任意步骤。

one work-item → one C element一个工作项 → 一个 C 元素 host submits work主机提交工作 GPU executes compiled ISAGPU 执行已编译 ISA
A · CPU
B · CPU
C · EXPECT
Step 1 of 10 · Define the problem

Step 00 · question · no GPU yet第 00 步 · 题目 · GPU 尚未参与

First decide what “correct” means.先确定什么叫“算对了”。

Before touching the ROCm stack, calculate one element by hand. This gives the CPU a correctness oracle for the value that eventually returns from the GPU.先不碰 ROCm 技术栈,手算一个元素。这样数据从 GPU 回来时,CPU 才有一个可对照的正确答案。

Code / 题目

C[row,col] = Σ A[row,k] × B[k,col]

C[0,0] = 1×5 + 2×7 = 19
C[0,1] = 1×6 + 2×8 = 22
C[1,0] = 3×5 + 4×7 = 43
C[1,1] = 3×6 + 4×8 = 50

State / 状态变化

No fixed test没有固定测试A, B and expected C on CPUCPU 上有 A、B 与期望 C

Why / 为什么

A tiny input makes every number inspectable. It teaches execution semantics; it does not demonstrate GPU speed.小输入让每个数都能人工检查。它适合学习执行语义,但不能证明 GPU 更快。

Observe / 如何观察

Prediction: [19, 22, 43, 50]. Do not open the stack yet.先写下预测:[19, 22, 43, 50]。此时无需看技术栈。

01 / 10
Open the complete HIP program, production shortcut and source trail展开完整 HIP 程序、生产实现捷径与技术依据
#include <hip/hip_runtime.h>
#include <array>
#include <cassert>
#include <cstdlib>
#include <iostream>

void check(hipError_t error) {
  if (error != hipSuccess) {
    std::cerr << hipGetErrorString(error) << std::endl;
    std::exit(1);
  }
}

__global__ void matmul2(const float* A, const float* B, float* C) {
  int row = blockIdx.y * blockDim.y + threadIdx.y;
  int col = blockIdx.x * blockDim.x + threadIdx.x;
  if (row < 2 && col < 2) {
    float sum = 0.0f;
    for (int k = 0; k < 2; ++k)
      sum += A[row * 2 + k] * B[k * 2 + col];
    C[row * 2 + col] = sum;
  }
}

int main() {
  std::array<float, 4> hA{1, 2, 3, 4};
  std::array<float, 4> hB{5, 6, 7, 8};
  std::array<float, 4> hC{};
  constexpr size_t bytes = 4 * sizeof(float);
  float *dA = nullptr, *dB = nullptr, *dC = nullptr;

  check(hipSetDevice(0));
  check(hipMalloc(reinterpret_cast<void**>(&dA), bytes));
  check(hipMalloc(reinterpret_cast<void**>(&dB), bytes));
  check(hipMalloc(reinterpret_cast<void**>(&dC), bytes));
  check(hipMemcpy(dA, hA.data(), bytes, hipMemcpyHostToDevice));
  check(hipMemcpy(dB, hB.data(), bytes, hipMemcpyHostToDevice));

  hipLaunchKernelGGL(matmul2, dim3(1, 1), dim3(2, 2), 0, 0,
                     dA, dB, dC);
  check(hipGetLastError());
  check(hipDeviceSynchronize());
  check(hipMemcpy(hC.data(), dC, bytes, hipMemcpyDeviceToHost));

  assert((hC == std::array<float, 4>{19, 22, 43, 50}));
  std::cout << "PASS: [" << hC[0] << ", " << hC[1]
            << ", " << hC[2] << ", " << hC[3] << "]"
            << std::endl;

  check(hipFree(dA));
  check(hipFree(dB));
  check(hipFree(dC));
}

Build and run构建与运行

hipcc --offload-arch=<your-gfx-arch> matmul2.hip -o matmul2 && ./matmul2

Production shortcut: rocBLAS生产实现捷径:rocBLAS

For a real GEMM, use a tuned library such as rocBLAS instead of this naive kernel. That replaces Step 05's handwritten kernel choice; it does not bypass HIP, ROCr or the driver. rocBLAS APIs are column-major by default, so row-major operands require careful layout handling.真实 GEMM 应使用 rocBLAS 等调优库,而不是这个朴素 kernel。它替换的是第 05 步的手写 kernel 选择,并不会绕过 HIP、ROCr 或驱动。rocBLAS API 默认按列主序解释矩阵,因此行主序输入必须正确处理布局。

Official source trail官方技术依据

HIP · matrix multiplication tutorial HIP · programming and execution model ROCr · user-mode HSA runtime Linux AMDGPU · user queues and doorbells rocBLAS · GEMM API reference
00

Now zoom out to the whole system现在再放大到整个系统

use the case above as your anchor以上面的案例作为阅读锚点
Highlight a path选择一条路径
The ROCm stack as runtime, build-time and observability paths Nine clickable layer nodes arranged in three zones. Runtime, build and observability controls highlight different relationships; KFD appears on a dashed setup branch rather than the per-dispatch hot path. CONSUMERS生态与应用 PROGRAMMING SURFACE编程表面 SYSTEM RUNTIME → KERNEL → SILICON系统运行时 → 内核 → 芯片 USER SPACE KERNEL / HW CODE OBJECT TRACE PLANE /dev/kfd · SETUP / EXCEPTIONS MAPPED MMIO · NO SYSCALL 08 Tools trace · profile · debug 追踪 · 分析 · 调试 07 Frameworks PyTorch · JAX · vLLM 09 Applications train · simulate · infer 训练 · 模拟 · 推理 06 Compiler Clang · LLVM · comgr 04 HIP the API you write 你直接编写的 API 05 Libraries rocBLAS · MIOpen · RCCL OUTER HOST ELF host .text .hip_fatbin gfx90agfx942 03 ROCr / HSA AQL · signals · agents 02 KFD / amdgpu GPUVM · mapped doorbell 01 GPU hardware CU · SIMD · HBM / VRAM
Active reading当前阅读路径

A tensor operation descends through the framework and tuned libraries, crosses HIP and ROCr, then becomes an AQL packet consumed by the GPU. KFD is crucial for setup, but not entered for every dispatch.一次张量运算经框架与调优库下行,穿过 HIP 和 ROCr,最终变成 GPU 消费的 AQL 包。KFD 对建立队列至关重要,但并不会在每次派发时都进入。

The compiler is a side path, not a rung in every launch. Clang and the AMDGPU back end turn HIP device code into a gfx-specific code object, which the runtime later loads.编译器是一条侧路,不是每次启动必经的台阶。Clang 与 AMDGPU 后端把 HIP 设备代码编成特定 gfx 的 code object,运行时再将它装入 GPU。

Profilers and debuggers form a cross-cutting plane. They collect API, queue, kernel and hardware-counter evidence from several layers instead of belonging to one ordinary runtime hop.性能分析器与调试器是一张横切平面:它们同时从 API、队列、kernel 与硬件计数器收集证据,并不只是运行时链条中的普通一跳。

01

Bottom-up layer reference自底向上的逐层参考

orientation reverses here: hardware → user这里反转方向:从硬件读向用户
01

Hardware & Platform硬件与平台

silicon

The compute units, memory and interconnect that everything above exists to reach. The GPU's gfx target ID is the fact the whole stack keys off. 计算单元、显存与互连 —— 上面所有层的存在都是为了到达这里。GPU 的 gfx 目标编号是整个栈的关键标识。

Data center (Instinct)数据中心

  • gfx950
  • gfx942
  • gfx90a
  • gfx908
  • CDNA 3 / 4

Desktop & APU桌面与 APU

  • gfx1201
  • gfx1200
  • gfx1100
  • gfx1151
  • gfx1103
  • RDNA 3 / 4, Ryzen AI

Inside the die芯片内部

  • Compute Unit
  • SIMD
  • Matrix cores
  • LDS
  • Infinity Cache

Memory & fabric内存与互连

  • HBM3E
  • GDDR6
  • PCIe Gen5
  • Infinity Fabric
  • XGMI

A binary built for gfx942 will not run on gfx1100. Run rocminfo first — the target name it prints is what you pass to --offload-arch. gfx942 编译的二进制不能跑在 gfx1100 上。先运行 rocminfo,它打印的目标名就是你要传给 --offload-arch 的值。

02

Kernel Driver & KFD内核驱动与 KFD

kernel space

The only code in the stack that runs in kernel space. It enumerates the device, owns GPU page tables, creates hardware queues, and hands your process a doorbell it can write to directly. 整个栈中唯一运行在内核态的部分:枚举设备、管理 GPU 页表、创建硬件队列,并把一个 doorbell 交给你的进程直接写。

Drivers驱动

  • amdgpu
  • amdkfd
  • DRM / KMS
  • upstream + DKMS

Device nodes设备节点

  • /dev/kfd
  • /dev/dri/renderD*
  • ioctl()

Memory & scheduling内存与调度

  • GPUVM page tables
  • SVM / IOMMU
  • HQD
  • MES / HWS
  • doorbells

Thin user-space shim用户态薄封装

  • libhsakmt
  • a.k.a. ROCt

libhsakmt is the wrapper that turns ROCr calls into /dev/kfd ioctls. It lives inside the ROCR-Runtime repository now, not as a separate project. libhsakmt 负责把 ROCr 的调用翻译成 /dev/kfd 的 ioctl。它现在已并入 ROCR-Runtime 仓库,不再是独立项目。

03

ROCr — HSA System RuntimeROCr 系统运行时

user space

AMD's implementation of the HSA runtime specification, and the lowest portable API in the stack. It exposes queue, agent and signal primitives; HIP/CLR uses them to publish an AQL packet into a queue the GPU reads on its own. AMD 对 HSA 运行时规范的实现,也是栈里最低的可移植 API。它提供队列、agent 与 signal 原语;HIP/CLR 利用这些原语把 AQL 包发布到 GPU 会自行读取的队列中。

The library运行时库

  • libhsa-runtime64.so
  • hsa_*() API
  • ROCR-Runtime

Dispatch任务派发

  • AQL packets
  • user-mode queues
  • architected dispatch
  • doorbell

Synchronisation同步

  • HSA signals
  • barrier packets

Memory & topology内存与拓扑

  • fine-grained
  • coarse-grained
  • agents
  • rocminfo

"Architected dispatch" lets the GPU command processor consume a defined packet format directly. Once the queue is ready, steady-state dispatch normally needs no per-launch submit ioctl; the kernel driver still manages queue lifetime, memory faults and recovery. "Architected dispatch"(架构化派发)让 GPU 命令处理器直接消费约定格式的包。队列就绪后,稳态派发通常无需逐次调用提交 ioctl;内核驱动仍管理队列生命周期、内存缺页与恢复。

04

HIP — Programming LayerHIP 编程层

the API you write

The interface almost everyone actually programs against. HIP is deliberately CUDA-shaped, so porting is mechanical rather than a rewrite — and the same source compiles for both vendors. 绝大多数人真正编写的接口。HIP 刻意做成与 CUDA 同形,因此移植是机械替换而非重写,同一份源码还能同时编译到两家硬件。

API surfaceAPI 表面

  • hipMalloc
  • hipMemcpy
  • hipLaunchKernelGGL
  • hipStream_t
  • hipEvent_t

Implementation (CLR)实现(CLR)

  • hipamd
  • rocclr
  • opencl
  • libamdhip64.so

Porting from CUDA从 CUDA 移植

  • HIPIFY
  • hipify-perl
  • hipify-clang
  • cuda* → hip*

Sibling models其他编程模型

  • OpenMP offload
  • OpenCL
  • SYCL
  • Kokkos / RAJA
  • Triton

CLR is where HIP stops being a header and becomes a runtime: hipamd implements the HIP spec, rocclr is the shared layer under both HIP and OpenCL, and it calls ROCr underneath. CLR 是 HIP 从头文件变成运行时的地方:hipamd 实现 HIP 规范,rocclr 是 HIP 与 OpenCL 共用的底层,再往下调用 ROCr。

05

Math & Performance Libraries数学与性能库

don't hand-write these

Tuned kernels for the operations you would otherwise write badly: GEMM, convolution, FFT, sparse, reductions, collectives. Reaching for these instead of a hand kernel is usually the single biggest perf decision. 为那些你自己写往往写不好的运算提供调优 kernel:GEMM、卷积、FFT、稀疏、归约、集合通信。用库而非手写 kernel,通常是性能上最重要的一个决定。

Dense & sparse linear algebra稠密与稀疏线性代数

  • rocBLAS
  • hipBLAS
  • hipBLASLt
  • rocSOLVER
  • hipSOLVER
  • rocSPARSE
  • hipSPARSE
  • hipSPARSELt

Deep-learning kernels深度学习算子

  • MIOpen
  • Composable Kernel
  • rocWMMA
  • hipDNN (beta)

Primitives, FFT & RNG基础原语 / FFT / 随机数

  • rocPRIM
  • hipCUB
  • rocThrust
  • rocFFT
  • hipFFT
  • rocRAND
  • hipRAND

Communication, media & I/O通信 / 多媒体 / I-O

  • RCCL
  • rocSHMEM
  • rocDecode
  • rocJPEG
  • hipFile

The naming rule: roc* is the AMD-native implementation; hip* is a thin portable wrapper that dispatches to roc* on AMD and to the cuBLAS-family on NVIDIA. Write against hip* if the code must travel. 命名规则:roc* 是 AMD 原生实现;hip* 是可移植薄封装,在 AMD 上转发到 roc*,在 NVIDIA 上转发到 cuBLAS 系列。代码要跨平台就用 hip*

06

Compiler Toolchain编译工具链

source → ISA

One source file, two compilations: host code for x86-64 and device code for every gfx target you asked for, bundled into a single fat binary the runtime unpacks at load time. 一份源码,两次编译:主机端编到 x86-64,设备端为你指定的每个 gfx 目标各编一份,再打包进同一个 fat binary,由运行时在加载时取出。

Compilers编译器

  • amdclang++
  • hipcc
  • ROCm LLVM
  • SPIRV-LLVM-Translator

Code generation代码生成

  • AMDGPU back end
  • LLVM IR
  • CDNA / RDNA ISA
  • register allocation

Linking & packaging链接与打包

  • code object (ELF)
  • clang-offload-bundler
  • device-libs (OCML / OCKL)
  • comgr

Reading the output查看产物

  • llvm-objdump -d
  • llvm-readobj --offloading
  • --save-temps

If you want to see what the GPU actually executes, this is the layer: llvm-objdump --disassemble on the extracted code object gives you real ISA, not IR. 想看 GPU 究竟执行了什么,就从这一层入手:对取出的 code object 执行 llvm-objdump --disassemble,得到的是真实 ISA 而非中间表示。

07

AI Frameworks & EcosystemAI 框架与生态

validated at 7.14.0

Frameworks that depend on layers 4–6 for execution, optimized kernels and build/JIT support. Because the HIP back end keeps the CUDA-shaped API, model code usually runs unchanged — torch.cuda still works, and still means "the AMD GPU". 这些框架依赖第 4–6 层提供执行、调优 kernel 与编译/JIT 支持。由于 HIP 后端保持了与 CUDA 同形的 API,模型代码通常无需改动 —— torch.cuda 依然可用,指的就是那块 AMD GPU。

Training & general训练与通用

  • PyTorch 2.12 / 2.11 / 2.10
  • JAX 0.10 / 0.9.1
  • Triton

Inference & serving推理与服务

  • vLLM 0.23
  • SGLang 0.5.13
  • llama.cpp

Graph & model formats图与模型格式

  • MIGraphX 2.16
  • ONNX Runtime 1.23.2
  • Hugging Face

Expansion SDKs扩展 SDK

  • ROCm-DS
  • ROCm-CV
  • ROCm-LS
  • optional, on top of Core SDK

TensorFlow was long supported but no longer appears in AMD's validated compatibility matrix — treat PyTorch, JAX and the inference servers as the maintained paths. TensorFlow 曾长期受支持,但已不在 AMD 官方验证的兼容性矩阵中 —— 应把 PyTorch、JAX 与推理服务栈视为当前维护的主路径。

08

Profiling, Debugging & Control性能分析、调试与管理

cuts across layers 1–9

Not a layer you sit on — a layer you look through. These are how you find out what the other eight are doing, from a single kernel's occupancy up to fabric traffic between eight GPUs. 这不是你"站在上面"的一层,而是你"透过它去看"的一层:从单个 kernel 的占用率,到八卡之间的互连流量,都靠它们观测。

Profilers性能分析器

  • rocprofv3
  • rocprof-compute
  • rocprof-sys
  • ex-Omniperf / Omnitrace

Debuggers调试器

  • rocgdb
  • ROCdbgapi
  • ROCR Debug Agent

Monitoring & inventory监控与查询

  • amd-smi
  • rocminfo
  • hipinfo
  • RDC
  • rocm-smi deprecated

Validation验证

  • RVS
  • TransferBench
  • replaces ROCm Bandwidth Test

Start with rocprofv3 for a kernel trace, then move to rocprof-compute when you need roofline and per-CU counters. Omniperf and Omnitrace were renamed in ROCm 6.3 — old tutorials still use the old names. 先用 rocprofv3 抓 kernel trace,需要 roofline 与 CU 级计数器时再上 rocprof-compute。Omniperf 与 Omnitrace 已在 ROCm 6.3 改名,旧教程里仍是旧名字。

09

Applications应用层

why the other eight exist

The workloads the stack was built to carry — and the deployments that prove it carries them at scale. 整个软件栈存在的理由,以及证明它确实能撑起规模的真实部署。

AI人工智能

  • LLM pre-training
  • fine-tuning
  • large-scale inference

HPC & science高性能计算与科学

  • CFD
  • molecular dynamics
  • weather & climate
  • seismic

Media & vision多媒体与视觉

  • video decode pipelines
  • image preprocessing
  • render compute

Deployed at scale规模化部署

  • Frontier
  • El Capitan
  • LUMI
  • exascale, on Instinct
02

Advanced sequence diagrams进阶时序图

open when you want exact control flow需要精确控制流时再展开
Open the launch and compilation deep dives展开启动与编译的深度图解2 diagrams2 张图
Fig. 1

Life of a kernel launch一次 kernel 启动的完整路径

GPU HARDWARE EVERY LAUNCH — 每次启动 ONCE, AT SETUP — 仅建立一次 Your code hipLaunchKernelGGL(myKernel, …) HIP runtime · libamdhip64.so hipamd + rocclr (CLR) ROCr · libhsa-runtime64.so queue + agent + signal primitives AQL queue in mapped memory 64-byte packet, write index++ Doorbell write (MMIO) calls into the runtime prepare / publish dispatch writes AQL dispatch packet rings the doorbell no syscall — never enters the kernel Command processor (MES) fetches it CUs · SIMDs run the workgroups HSA completion signal decremented by the hardware kernel finishes hipStreamSynchronize() returns libhsakmt (ROCt) hsaKmtCreateQueue() queue creation USER SPACE KERNEL SPACE ioctl() amdkfd · inside amdgpu allocates the hardware queue descriptor, maps queue + doorbell into your address space maps the doorbell page
Steady-state direct dispatch: orange shows packet publication and the doorbell write; blue shows queue setup. This path normally avoids a per-launch submit ioctl. It does not remove the kernel driver from execution: memory faults, migration, queue eviction and recovery can still involve amdkfd and affect latency or progress. Investigate both runtime and driver events when work stalls or slows down. 稳态直接派发:橙色表示发布包与写 doorbell,蓝色表示队列建立。此路径通常省去逐次提交的 ioctl,但不意味着执行过程中不再涉及内核驱动:内存缺页、迁移、队列驱逐和恢复仍可能进入 amdkfd,并影响延迟或任务推进。排查卡住或变慢时,应同时检查运行时与驱动事件。
Fig. 2

One source file, two targets一份源码,两套目标代码

kernel.hip host + device amdclang++ splits the source device LLVM IR + device-libs AMDGPU back end CDNA / RDNA ISA code object · ELF --offload-arch=gfx942 host host pass → x86-64 object ordinary C++ compilation clang-offload-bundler outer host ELF .hip_fatbin → gfx images
At run time the HIP runtime asks which GPU is present, then loads the matching code object from the host ELF's embedded .hip_fatbin section — via comgr if it has to compile or link anything on the spot. A "no kernel image is available" error almost always means no embedded code object matches the gfx target that rocminfo reports. 运行时,HIP runtime 先识别当前 GPU,再从主机 ELF 内嵌的 .hip_fatbin 段中装入匹配的 code object(需要即时编译或链接时通过 comgr)。报错 "no kernel image is available" 通常意味着:没有任何内嵌 code object 匹配 rocminfo 报告的 gfx 目标。
03

Suggested learning path建议的学习路径

bottom-up, one artefact to touch at each step自下而上,每步都有一个可以动手的对象
STEP 01

Identify your hardware先认清硬件

Learn what a gfx target is and find yours. Everything downstream depends on it.搞清 gfx 目标编号是什么,并找到自己的那个。后面每一步都依赖它。

rocminfo | grep gfx
STEP 02

Look at the driver观察驱动

Confirm amdgpu is loaded and the compute node exists. Read the KFD topology the driver exports.确认 amdgpu 已加载、计算节点存在,并读取驱动导出的 KFD 拓扑信息。

ls /dev/kfd && ls /sys/class/kfd/kfd/topology/nodes/
STEP 03

Write one HIP kernel写第一个 HIP kernel

Vector add, by hand: allocate, copy, launch, synchronise, free. Do not use a library yet.手写一个向量加法:分配、拷贝、启动、同步、释放。先别用任何库。

hipcc --offload-arch=gfx942 vadd.hip
STEP 04

Open the binary打开产物

Extract the code object and read the ISA. This is where the compiler layer stops being abstract.取出 code object 并阅读 ISA。到这一步,编译器那一层才不再抽象。

llvm-objdump --disassemble vadd.o
STEP 05

Swap in a library换用数学库

Rewrite a hand-written GEMM using rocBLAS, then measure the difference. Learn the roc* vs hip* rule.rocBLAS 重写手写 GEMM 并对比性能,同时理解 roc*hip* 的区别。

-lrocblas
STEP 06

Profile it做性能分析

Trace the kernel, read occupancy and memory throughput, then go back and change one thing.抓取 kernel trace,读占用率与访存带宽,然后回头只改一个变量再测。

rocprofv3 --kernel-trace -- ./vadd
STEP 07

Come back up to the frameworks回到框架层

Run PyTorch on ROCm and recognise every layer it is standing on. That recognition is the whole point of this sheet.在 ROCm 上跑 PyTorch,并认出它脚下的每一层。这份图的全部意义就在于此。

torch.cuda.is_available() # True, on AMD